The logic required to implement the MII transmitter logic
is illustrated in Figure 1 .
mii_tx_clk is provided by the external PHY device connected to the MII. As
shown, this is placed onto regional (BUFR) clock routing to provide the clock for all
transmitter logic, both within the core and for the user-side logic which connects to the TX
AXI4-Stream interface of the core. Alternatively, for fully flexible I/O
placement the BUFR in Figure 1 can be
replaced with a global clock buffer (BUFG). To perform this, edit the core instance
unencrypted HDL file, <component_name_mii_if> present in the core instance
synth/physical directory, and replace the BUFR instance on mii_tx_clk input with a
BUFG. For more details on editing core instance unencrypted HDL files, see the Synthesis and Implementation.
To match the user data rate (which uses an 8-bit datapath)
and the MII (which uses a 4-bit datapath), the TX AXI4-Stream interface is
throttled, using tx_axis_mac_tready , under control of the MAC to limit data transfers
to every other cycle.
Figure 1 also illustrates how to use the physical transmitter interface of the core to create an external MII. The signal names and logic shown in this figure exactly match those delivered with the core. Figure 1 shows that the output transmitter signals are registered in device IOBs before driving them to the device pads.