The logic required to implement the MII receiver logic is
also illustrated in Figure 1 .
mii_rx_clk is provided by the external PHY device connected to the MII. As
illustrated, this is placed on regional (BUFR) clock routing to provide the clock for all
receiver logic, both within the core and for the user-side logic which connects to the RX AXI4-Stream interface of the TEMAC.
Alternatively, for fully flexible I/O
placement, the BUFR in Figure 1 can be replaced with a global clock buffer (BUFG). To perform this edit
the core instance unencrypted HDL file, <component_name_mii_if> present in the core instance synth/physical directory,
and replace the BUFR instance on mii_rx_clk input with a
BUFG. For more details on editing core instance unencrypted HDL files, see the Synthesis and Implementation.
To match the user data rate, which uses an 8-bit datapath
and the MII, which uses a 4-bit datapath, the RX AXI4-Stream interface is
throttled, using rx_axis_mac_tvalid , under control of the MAC to limit data transfers
to every other cycle.
Figure 1 also illustrates how to use the physical receiver interface of the core to create an external MII. The signal names and logic shown in this figure exactly match those delivered with the example design. Figure 1 shows that the input receiver signals are registered in device IOBs before routing them to the core.