| Address (Hex) | Default Value | Type | Description |
|---|---|---|---|
| 0x600 | 0x00 | RO | Interrupt Status Register. Indicates the status of an interrupt. |
| 0x610 | 0x00 | RO | Interrupt Pending Register. Indicates the pending status of an interrupt. Bits in this register are only set when the corresponding bits in IER and ISR are set. |
| 0x620 | 0x00 | R/W | Interrupt Enable Register. Indicates the enable state of an interrupt. Writing a 1 to any bit enables that particular interrupt. |
| 0x630 | 0x00 | WO | Interrupt Clear Register. Writing a 1 to any bit of this register clears that particular interrupt. |
Bit[0] of all interrupt registers is used to
indicate the MDIO Transaction complete interrupt and is asserted only when the core is
generated with the MDIO interface. Bits[3:1] are used for AVB interrupts and are asserted
only when the core is generated with AVB feature. Bit[1] is used to indicate interrupt_ptp_tx , Bit[2] is used to indicate interrupt_ptp_rx, and Bit[3] is used to indicate interrupt_ptp_timer. Bits[31:4] are Reserved.