In this implementation, a BUFIO is used to provide the lowest form of clock routing delay from the input clock to input GMII RX signal sampling at the device IOBs. However, this creates placement constraints, a BUFIO capable clock input pin must be selected, and all other input GMII RX signals must be placed in the respective BUFIO region. Refer the 7 Series FPGAs Clocking Resources User Guide (UG472).
The input clock is also placed onto regional clock routing using the BUFR component as illustrated in Figure 1 . This regional clock then provides the clock for all receiver logic, both within the core and for the user-side logic which connects to the receiver AXI4-Stream interface of the core.
Alternatively, for fully flexible I/O placement, the BUFR
in Figure 1 can be replaced with a
global clock buffer (BUFG). To perform this, edit the core instance unencrypted HDL file,
<component_name_gmii_if> present in the core instance synth/implementation
directory, and replace the BUFR instance on gmii_rx_clk with a BUFG. For more
details on editing core instance unencrypted HDL files, see Synthesis and Implementation.
The IODELAY elements can be adjusted to fine-tune the setup
and hold times at the GMII IOB input flip-flops. This meets the input setup and hold
constraints at all three Ethernet speeds. The delay is applied to the IODELAY element using
constraints in the XDC which can be edited if desired. See Constraining the Core.
Closely linked to the clock logic is the use of the rx_enable clock enable
derivation. This must be provided to the Ethernet MAC core level. All user logic uses the AXI4-Stream interface handshaking to throttle the data to allow for the differing
data widths between the 4-bit MII and the core 8-bit user datapath.