DEMO Mode - 9.0 English - PG051

The demonstration test bench performs the following tasks:

• Input clock signals are generated.
• A reset is applied to the example design.
• The required speed is selected using mac_speed and update_speed
• The MDIO stimulus/response block responds to a read with all 1s – to indicate no PHY is present.
• Four frames are pushed into the GMII/MII or RGMII receiver interface at the fastest MAC speed supported:
• The first frame is a minimum length frame.
• The second frame is a type frame.
• The third frame is an errored frame.
• The fourth frame is a padded frame.
• The frames received at the GMII/MII or RGMII transmitter interface are checked against the stimulus frames to ensure data is the same. The monitor process takes into account the source/destination address field and FCS modifications resulting from the address swap module.
• If either the Tri-speed or MII configurations have been selected, mac_speed is updated to run at the next fastest available speed. This is 100 Mbps or 10 Mbps respectively. update_speed is then pulsed.
• The MDIO stimulus/response block responds to a read with all 1s – to indicate no PHY is present.
• The same four frames are then sent to the MII/GMII or RGMII interface and checked against the stimulus frames.
• If the Tri-speed configuration has been selected, mac_speed is updated to run at 10 Mbps. update_speed is then pulsed.
• The MDIO stimulus/response block responds to a read with all 1s – to indicate no PHY is present.
• The same four frames are then sent to the MII/GMII or RGMII interface and checked against the stimulus frames.
• For the Tri-speed configuration, the speed is then changed back to 1 Gbps and the same four frames are sent and checked for a final time. This tests the speed switching between 1 Gbps and 10/100 Mbps in both directions.