When multiple instances of the core are instantiated in a design, transmitter clock resources can be shared across all core instances, receiver clock resources cannot be shared and are independent for each core instance.
The following figure shows clock
resource sharing across multiple instantiations of the core when using GMII at 1 Gbps. For
all instantiations, gtx_clk can be shared between multiple
cores, resulting in a common clock domain across the device. The receiver clocks cannot be
shared. Each core is provided with its own local version of gmii_rx_clk from the connected external PHY device as shown in the following figure
.
The upper core instance has been
generated with the Shared Logic option enabled, and for the GMII this instantiates an
IDELAYCTRL as illustrated. The other core instances have been generated without the Shared
Logic option enabled (because only a single instance of an IDELAYCTRL is usually required
per design). The following figure illustrates three cores. However, more can be added using
the same principle. This is done by instantiating further cores without the Shared Logic
option and sharing gtx_clk across all instantiations. The
receiver clock, which cannot be shared, is unique for every instance of the core.