The following table shows the relationship between the fields in the AMD Vivado™ IDE and the user parameters (which can be viewed in the Tcl Console).
| AMD Vivado™ IDE Parameter/Value | User Parameter/Value | Default Value |
|---|---|---|
| MDIO | ETHERNET_BOARD_INTERFACE | Custom |
| DIFFCLK | DIFFCLK_BOARD_INTERFACE | Custom |
| MDIO | MDIO_BOARD_INTERFACE | Custom |
| Standard | Standard | 1000BASEX |
| Data Rate | MaxDataRate | 1G |
| Physical Interface | Physical_Interface | Transceiver |
| Rx Gmii Clk Src | RxGmiiClkSrc | TXOUTCLK |
| MDIO Management Interface | Management_Interface | true |
|
MDIO Management Interface for external PHY |
Ext_Management_Interface | false |
| Auto Negotiation | Auto_Negotiation | true |
| SGMII Mode | SGMII_Mode | 10_100_1000 |
| SGMII PHY Mode | SGMII_PHY_Mode | false |
| Select Ethernet | EMAC_IF_TEMAC | TEMAC |
| Shared Logic | SupportLevel |
Include_Shared_Logic_in_ Example_Design |
| GT in Example Design | GTinEx | false |
| Additional transceiver control and status ports | TransceiverControl | false |
| Reference Clock Frequency (MHz) | RefClkRate | 125 |
| LVDS Reference Clock | LvdsRefClk | 125 |
| DRP Clock Frequency (MHz) | DrpClkRate | 50.0 |
| Number of Lanes | NumOfLanes | 1 |
| Tx In Upper Nibble | Tx_In_Upper_Nibble | 1 |
| TxLane0 Placement | TxLane0_Placement | DIFF_PAIR_0 |
| RxLane0 Placement | RxLane0_Placement | DIFF_PAIR_0 |
| TxLane1 Placement | TxLane1_Placement | DIFF_PAIR_1 |
| RxLane1 Placement | RxLane1_Placement | DIFF_PAIR_1 |
| EnableAsyncSGMII | EnableAsyncSGMII | FALSE |
| Transceiver Location | GT_Location | X0Y0 |
| GT Type | GT_Type | GTH |