The following figure shows the transceiver connections for UltraScale+/UltraScale devices. It shows the connectivity of clocking logic with the encrypted core and transceiver channel. The internal signal names of GT_CHANNEL or the encrypted RTL might not exactly correspond to the block level port names. For connectivity purposes at the block level see Port Descriptions. For shared logic connectivity guidelines see Clock Sharing Across Multiple Cores with Transceivers and FPGA Logic Elastic Buffer.
The differential reference clock selected through the Vivado IDE is routed directly to the UltraScale FPGA transceiver. The transceiver is configured to output a
version of this clock (125 MHz for 1 Gb/s, 312.5 MHz for 2.5 Gb/s) on the txoutclk port; txoutclk is
then routed to a BUFG_GT to generate userclk (62.5,125
MHz in 1G mode and 312.5,156.25 MHz in 2.5G mode), userclk2 (125 MHz in 1G mode, 312.5 MHz in 2.5G mode) and placed onto
global clock routing. These clocks are input back into the transceiver on the user
interface clock ports usrclk and usrclk2. The clocking logic is included in a separate
module <component_name>_clocking which is
instantiated in the <component_name>_support
module.
Transceiver files are generated on runtime through UltraScale+/UltraScale gtwizard. See the UltraScale Architecture GTH Transceivers User Guide (UG576), the UltraScale Architecture GTY Transceivers User Guide (UG578), and the UltraScale FPGAs Transceivers Wizard LogiCORE IP Product Guide (PG182) for details on the supporting logic and files generated.