The core is designed to integrate with 7 series and Zynq 7000 FPGA transceivers. The following figure shows the transceiver connections for AMD Virtex™ 7, AMD Kintex™ 7and Zynq 7000 devices. AMD Virtex™ 7 devices support both the GTX and GTH transceivers; AMD Kintex™ 7 and Zynq 7000 devices support the GTX transceiver. For AMD Artix™ 7devices, the transceiver is connected as shown in the following figure; the supported transceiver is a GTP transceiver.
Both the following figures show the connectivity of the clocking logic with the
encrypted core and transceiver channel. The internal signal name of GT_CHANNEL or
Encrypted RTL might not exactly correspond to the block level port names. For
connectivity at the block level see Port Descriptions.
For shared logic connectivity guidelines see Clock Sharing Across Multiple Cores with Transceivers. Note
that in this case rxuserclk /
rxuserclk2 is unused in the core.
The 125 MHz differential reference clock is routed directly to the 7 series
FPGA transceiver. The transceiver is configured to output a version of this clock (62.5
MHz, 125 MHz for 2.5 Gb/s) on the txoutclk port; this
is then routed to a MMCM. From the MMCM, generated clocks (62.5 MHz, 125 MHz for 1 Gb/s;
156.25 MHz, 312.5 MHz for 2.5 Gb/s) are placed onto global clock routing and are input
back into the transceiver on the user interface clock ports txusrclk , and txusrclk2. The clocking logic
is included in a separate module <component_name>_clocking which is instantiated in the <component_name>_support module.
The two wrapper files immediately around the transceiver pair, gtwizard and gtwizard_gt
as shown in the following figure, are generated from the 7 series FPGA Transceiver wizard. These files apply all the Gigabit
Ethernet attributes. Consequently, these files can be regenerated by customers. See
Regeneration of 7 Series/Zynq 7000 Transceiver Files for more information.
A 500 ns wait time for reset is generated with respect to the system clock input in the <component_name>_gtwizard_init.v[hd] module. The STABLE_CLOCK_PERIOD attribute in this file has to be set to the period of the system clock.