Synchronous SGMII over LVDS Using Component Mode - Synchronous SGMII over LVDS Using Component Mode - 17.0 English - PG047

1G/2.5G Ethernet PCS/PMA or SGMII LogiCORE IP Product Guide (PG047)
Document_ID
PG047
Release_Date
2026-08-11
Version
17.0 English

The core can fully support SGMII using standard LVDS SelectIOtechnology logic resources. This enables direct connection to external PHY devices without the use of an FPGA transceiver. This implementation is shown in the following figure. The core does not supports 2.5G SGMII modes for the LVDS physical interface.

Figure 1. Core Block Diagram with Standard SelectIO Technology Support for SGMII Ethernet 1000BASE-X PCS/PMA or SGMII Page-1 Sheet.1 Sheet.2 Sheet.3 Sheet.4 Clocking Logic Clocking Logic Sheet.5 refclk125_p refclk125_p Sheet.6 refclk125_n refclk125_n Sheet.7 clk125 clk125 Sheet.8 clk104 clk104 Sheet.9 clk208 clk208 Sheet.10 clk625 clk625 Sheet.11 LVDS Transceiver LVDS Transceiver Sheet.12 Sheet.13 rxn rxn Sheet.14 rxp rxp Sheet.15 txn txn Sheet.16 txp txp Sheet.17 <component_name>_block <component_name>_block Sheet.18 <component_name>_example_design <component_name>_example_design Sheet.19 Encrypted RTL EncryptedRTL Sheet.20 Sheet.21 SGMII Adaptation Module SGMII Adaptation Module Sheet.22 Sheet.23 GMII-Style 8-bit I/F GMII-Style8-bit I/F Sheet.24 X12959 X12959 Standard Arrow.19 Standard Arrow.6 Standard Arrow.7 Standard Arrow.11 Standard Arrow.15 Standard Arrow.18 Standard Arrow.21 Standard Arrow.24 Standard Arrow.33 Standard Arrow.34 Standard Arrow Arrow - Standard.19 Arrow - Standard.22 Arrow - Standard.25 Standard Arrow.47 Standard Arrow.9
Note: For UltraScale devices, clocking logic generates 125, 312.5, and 625 MHz clocks respectively. Frequencies shown in the previous figure are applicable for 7 series devices.

The core netlist in this implementation is identical to that of the previous figure and all core netlist blocks are identical to those described in 1G/2.5G Ethernet PCS/PMA or SGMII Using a Device-Specific Transceiver.

As shown in the previous figure, the Hardware Description Language (HDL) example design for this implementation provides additional logic to form the LVDS transceiver. The LVDS transceiver block fully replaces the functionality otherwise provided by an UltraScale or 7 series FPGA transceiver. This is only possible at a serial line rate of 1.25 Gb/s. The following subsections describe the design requirements.