Synchronous SGMII over LVDS Transceiver Interface Ports - 17.0 English - PG047

1G/2.5G Ethernet PCS/PMA or SGMII LogiCORE IP Product Guide (PG047)
Document ID
PG047
Release Date
2025-12-19
Version
17.0 English

The following table shows the physical side interface ports for SGMII over LVDS when Shared Logic is included in the Example Design.

Table 1. Physical Side Interface Ports for SGMII over LVDS – Shared Logic in Example Design
Signal Direction Description
clk125m Input 125 MHz reference clock from IBUFDS.
txp Output Transmit differential
txn Output Transmit differential
rxp Input Receive differential
rxn Input Receive differential
clk104 Input 104 MHz clock derived from 125MHz input differential clock
clk208 Input 208 MHz clock derived from 125MHz input differential clock
clk625 Input 625 MHz clock derived from 125MHz input differential clock
mmcm_locked Input Indication from the MMCM that the outputs are stable

The following table describes the physical side interface ports when the core is configured with SGMII over LVDS when Shared Logic is included in the core.

Table 2. Physical Side Interface Ports for SGMII over LVDS with Shared Logic in the Core
Signal Direction Description
refclk125_p Input Differential 125 MHz clock synchronous to incoming SGMII serial data
refclk125_n Input Differential 125 Mhz clock synchronous to incoming SGMII serial data
clk125_out Output Single ended 125 MHz clock.
clk625_out Output 625 MHz clock
clk208_out Output 208 MHz clock
clk104_out Output 104 MHz clock
rst_125_out Output Output reset synchronous to 125 MHz clock.
mmcm_locked_out Output MMCM locked indication.
txp Output Transmit differential
txn Output Transmit differential
rxp Input Receive differential
rxn Input Receive differential
Note: The signal eye_mon_wait_time is given a lower value for ease in simulation. Actual implementation can tie it to 12'hFFF.