For comprehensive information about AMD Vivado™ simulation components, as well as information about using supported third-party tools, see the Vivado Design Suite User Guide: Logic Simulation (UG900).
Important: For cores targeting 7 series or
Zynq 7000 devices, UNIFAST libraries are not supported. AMD IP is tested and qualified with UNISIM libraries only.
All simulation sources are included that are required by the core. Simulation of PCS-PMA at the core level is not supported without the addition of a test bench (not supplied). Simulation of the example design is supported.
Note: EXAMPLE_SIMULATION generic is provided in
all modes to reduce simulation time. In simulation, the value of EXAMPLE_SIMULATION should be 1.
In implementation, the value of EXAMPLE_SIMULATION should be 0. To change the EXAMPLE_SIMULATION
attribute you need to run the following command before the generation of output products:
set_property CONFIG.EXAMPLE_SIMULATION {1} [get_ips <component_name>
]
Note: EXAMPLE_SIMULATION generic should be set
to 1 only for simulation; for synthesis this should be reset to 0.