The LVDS transceiver block fully replaces the functionality otherwise provided by a 7 series device transceiver. This is only possible at a serial line rate of 1.25 Gb/s. The following figure shows a block diagram of the LVDS transceiver for Zynq 7000 and 7 series devices. This is split up into several sub-blocks which are described in further detail in the following sections.
On the transmitter path, data sourced by the core netlist is routed through the 8B/10B Encoder to translate the 8-bit code groups into 10-bit data. The 10-bit data is then passed through the 10B6B Gearbox and the parallel data is then clocked out serially at a line rate of 1.25 Gb/s.
The receiver path has additional complexity. Serial data received at 1.25 Gb/s is routed in parallel to two IODELAYs and ISERDES. Logic is provided to find the correct sampling point in the eye monitor and Phy calibration blocks.
The 6-bit parallel data is fed to the 6B10B gearbox which converts it into 10-bit parallel data. Having recovered parallel data from the serial stream, the Comma Alignment module, next on the receiver path, detects specific 8B/10B bit patterns (commas) and uses these to realign the 10-bit parallel data to contain unique 8B/10B code groups. These code groups are then routed through the 8B/10B Decoder module to obtain the unencoded 8-bit code groups that the core netlist can accept.
The following files describe the top level of the hierarchal levels of the LVDS transceiver:
<project_dir>/<project_name>/<project_name>.srcs/sources1/ip/<component_name>/ synth/lvds_transceiver/<component_name>_lvds_transceiver.v[hd]