This logic, along with eye monitor and PHY calibration, is used to convert incoming serial data into 6-bit parallel data. See IODELAYs and RDES in the 7 Series FPGAs SelectIO Resources User Guide (UG471) for more information on these primitives.
This logic, along with eye monitor and PHY calibration, is used to convert incoming serial data into 6-bit parallel data. See IODELAYs and RDES in the 7 Series FPGAs SelectIO Resources User Guide (UG471) for more information on these primitives.