For clocking frequencies for the Vivado Design Suite, see Constraining the Core.
For clocking information on the client interface in SGMII mode, see Constraining the Core.
For clocking information on the PHY interface, see the following:
- For Asynchronous LVDS Clocking, see Asynchronous LVDS Transceiver for Versal devices.
- For 1000BASE-X or 2500BASE-X, see 1000BASE-X or 2500BASE-X with Transceivers.
- For SGMII and Dynamic Switching, see SGMII/Dynamic Switching with Transceivers.
- For System Synchronous SGMII over LVDS, see SGMII LVDS Clocking Logic.