The block level connects together all of the components for a single SGMII port. These are:
- A core netlist (introduced in 1G/2.5G Ethernet PCS/PMA or SGMII Using a Device-Specific Transceiver).
- The Synchronous SGMII LVDS Transceiver for UltraScale Devices, connected to
the PHY side of the core netlist, to perform the SerDes functionality using the
Synchronous LVDS Method. Containing:
- Functionality for I/O functionality and gearbox modules in transmit and receive path for data width conversion.
- Functionality to find the right sampling point using eye monitor and phy calibration modules.
- The SGMII Adaptation Module top level,
connected to the Ethernet MAC (GMII) side of the core netlist, containing:
- The clock management logic required to enable the SGMII example design to operate at 10 Mb/s, 100 Mb/s, and 1 Gb/s.
- GMII logic for both transmitter and receiver paths; the GMII style 8-bit interface is run at 125 MHz for 1 Gb/s operation; 12.5 MHz for 100 Mb/s operation; 1.25 MHz for 10 Mb/s operation.