The core supports Asynchronous SGMII/1000BASE-X over LVDS using High Speed SelectIO logic resources in Native Mode for UltraScale / UltraScale+ devices.
For Versal devices, the Asynchronous SGMII/1000Base-X over LVDS is using the Advanced IO Wizard IP as a subcore module. This enables direct connection to an external PHY without using the FPGA transceiver. 2.5G data rates are not supported in this mode.