The following figure shows The Example design provided for Asynchronous
1000BaseX/SGMII over Versal device LVDS Implementation. Logic to generate
Input clocks (125 MHz Core Clock, PLL input clock and CTRL clock) for the core and the
RIU reset state machine are provided in the example design.
Figure 1. Example design for Asynchronous SGMI/1000BaseX over LVDS (Versal)
Figure 2. Example design for Synchronous SGMI/1000BaseX over LVDS (Versal Gen2 Devices)