Asynchronous 1000Base-X/SGMII over LVDS Example Design (Versal Devices) - Asynchronous 1000Base-X/SGMII over LVDS Example Design (Versal Devices) - 17.0 English - PG047
The following figure shows The Example design provided for Asynchronous
1000Base-X/SGMII over Versal device LVDS Implementation.
Logic to generate Input clocks (125 MHz Core Clock, PLL input clock and CTRL clock) for
the core and the RIU reset state machine are provided in the example design.
Figure 1. Example Design for Asynchronous SGMI/1000Base-X over LVDS (Versal)
Figure 2. Example Design for Synchronous SGMI/1000Base-X over LVDS (Versal Adaptive SoC Gen 2 Devices)