Advanced IO PLL INPUT Clock - Advanced IO PLL INPUT Clock - 17.0 English - PG047

1G/2.5G Ethernet PCS/PMA or SGMII LogiCORE IP Product Guide (PG047)

Document_ID
PG047
Release_Date
2026-08-11
Version
17.0 English

Specifies the reference clock for the XPLL present in Advanced IO wizard sub-core. Valid values are 125, 156.25, 312.5 and 625. This option is shown instead of “LVDS Reference Clock Frequency” For AMD Versal™ devices.