At 100 Mb/s the operation of the core remains unchanged. It is the responsibility of the client logic (for example, an Ethernet MAC) to enter data at the correct rate. When operating at 100 Mb/s, every byte of the MAC frame (from preamble to the Frame Check Sequence field, inclusive) should be repeated for 10 clock periods to achieve the desired bit rate, as shown in the following figure. It is also the responsibility of the client logic to ensure that the interframe gap period is legal for the current speed of operation. Only when the core is connected to Ethernet MAC peripherals of the processing subsystem present in Zynq and Versal devices, the core takes care of converting the 4-bit MII interface to the 8 bits required by the core. In all other cases the core expects 8 bits from the client logic.
