At 100 Mb/s, the operation of the core is unchanged. When operating at a speed of 100 Mb/s, every byte of the MAC frame (from the preamble to the frame check sequence field, inclusive) is repeated for 10 clock periods to achieve the desired bit rate. See the following figure. Only when the core is connected to Ethernet MAC peripherals of the processing subsystem present in Zynq and Versal devices, the core will take care of converting the 8 bit from the core to 4-bit MII interface. In other cases, it is the responsibility of the client logic, for example an Ethernet MAC, to sample this data correctly.
Figure 1. GMII Data Reception at 100 Mb/s
