If a back channel is not possible,
serial channels can be initialized by driving the TX simplex
initialization with a set of timers. The timers must be designed
carefully to meet the needs of the system because the average time
for initialization depends on many channel specific conditions such
as clock rate, channel latency, skew between lanes, and noise.
C_ALIGNED_TIMER, C_BONDED_TIMER, and C_VERIFY_TIMER are timers used
for assertion of tx_aligned , tx_bonded , and tx_verify signals, respectively. These
timers use worst-case values obtained from corner case functional
simulations and implemented in the <component name>_core module.
Some of the initialization logic
in the Aurora 8B/10B module uses watchdog timers to prevent
deadlock. These watchdog timers are used on the RX side of the
channel, and can interfere with the proper operation of TX
initialization timers. If the RX simplex module goes from aligned , bonded
or verify , to reset , make sure that it is not because the
TX logic spend too much time in one of those states. If a
particularly long timer is required to meet the needs of the
system, the watchdog timers can be adjusted by editing the module.
For most cases, this should not be necessary and is not
recommended.
Aurora 8B/10B channels normally re-initialize only in the case of failure. When there is no back channel available, event-triggered re-initialization is impossible for most errors because, typically, the RX side detects the failure while the condition must be handled by the TX side. The solution is to make timer-driven TX simplex modules re-initialize on a regular basis. If a catastrophic error occurs, the channel is reset and running again after the next re-initialization period arrives. System designers should balance the average time required for re-initialization against the maximum time their system can tolerate an inoperative channel to determine the optimum re-initialization period for their systems.