Use Case 3: tx_system_reset and rx_system_reset assertion in a simplex core - 11.1 English - PG046

The following figure shows the simplex-TX core and simplex-RX core connected in a system. TX_IP and RX_IP could be in the same or multiple device(s).

Figure 1. System with Simplex Cores

The following figure shows the recommended procedure of tx_system_reset and rx_system_reset assertion in the simplex core.

1. tx_system_reset and rx_system_reset are asserted for at least six clock user_clk time periods.
2. tx_channel_up and rx_channel_up are deasserted after three user_clk cycles.
3. rx_system_reset is deasserted (or) released after tx_system_reset is deasserted. This ensures that the transceiver in the simplex-TX core starts transmitting initialization data much earlier and it enhances the likelihood of the simplex-RX core aligning to the correct data sequence.
4. rx_channel_up is asserted before tx_channel_up assertion. This condition must be satisfied by the simplex-RX core and simplex timer parameters (C_ALIGNED_TIMER, C_BONDED_TIMER and C_VERIFY_TIMER) in the simplex-TX core need to be adjusted to meet this criteria.
5. tx_channel_up is asserted when the simplex-TX core completes the Aurora 8B/10B protocol channel initialization sequence transmission for the configured time. Assertion of tx_channel_up last ensures that the simplex-TX core transmits the Aurora initialization sequence when the simplex-RX core is ready.

Figure 2. tx_system_reset and rx_system_reset Assertion in the Simplex Core