The following table describes the function of each of the status and control ports of the Aurora 8B/10B core. Table 1 describes the transceiver ports.
| Name | Direction | Clock Domain | Description |
|---|---|---|---|
|
channel_up/ tx_channel_up/ rx_channel_up |
Output | user_clk | Asserted when Aurora 8 B/10 B channel initialization is complete and the channel is ready for data transfer. tx_channel_up and rx_channel_up are only applicable to their respective simplex cores. |
|
lane_up[0:m –1]/ tx_lane_up[0:m –1]/ rx_lane_up[0:m –1]1 |
Output | user_clk | Asserted for each lane upon successful lane initialization, with each bit representing one lane. tx_lane_up[0:(m –1)] and rx_lane_up[0:(m –1)] are only applicable to their respective simplex cores. |
| frame_err | Output | user_clk | Channel frame/protocol error detected. This port is asserted for a single clock. Not available on simplex TX cores. |
|
hard_err/ tx_hard_err/ rx_hard_err |
Output | user_clk | Hard error detected (asserted until Aurora 8 B/10 B core resets). tx_hard_err and rx_hard_err are only applicable to their respective simplex cores. |
| soft_err | Output | user_clk | Soft error detected in the incoming serial stream. Not available on simplex TX core. |
|
reset/ tx_system_reset/ rx_system_reset |
Input | async | Resets the Aurora 8 B/10 B core (active-High). This signal must be asserted for at least six user_clk cycles. tx_system_reset and rx_system_reset are only applicable to their respective simplex cores. |
| gt_reset | Input | async |
The reset signal for the transceivers is connected to the top level through a debouncer. The gt_reset port should be asserted when the module is first powered up in hardware. This systematically resets all Physical Coding Sublayer (PCS) and Physical Medium Attachment (PMA) subcomponents of the transceiver. The signal is debounced using init_clk_in and must be asserted for six init_clk_in cycles. See the Reset section in the respective transceiver user guide for further details. |
| link_reset_out | Output | init_clk | Driven High if hot-plug count expires. |
| init_clk_in | Input | NA |
The init_clk_in port is required because user_clk stops when gt_reset is asserted. It is recommended that the frequency chosen for init_clk_in be lower than the GT Reference Clock input frequency. For UltraScale and UltraScale+ architecture designs: See UltraScale Architecture GTH Transceivers User Guide (UG576) for more details on the range of allowable frequency as updated in the GUI customization. This is also connected to the DRPCLK port of GTHE3/GTYE3/GTHE4/GTYE4 channel primitives. |
| tx_aligned 2 | Input | user_clk | Asserted when the RX channel partner has completed lane initialization for all lanes. Typically connected to rx_aligned. |
| tx_bonded 2 | Input | user_clk | Asserted when the RX channel partner has completed channel bonding. Not needed for single-lane channels. Typically connected to rx_bonded. |
| tx_verify 2 | Input | user_clk | Asserted when the RX channel partner has completed verification. Typically connected to rx_verify. |
| tx_reset 2 | Input | user_clk | Asserted when reset is required because of initialization status of RX channel partner. This signal must be synchronous to user_clk and must be asserted for at least one user_clk cycle. Typically connected to rx_reset. |
| rx_aligned 3 | Output | user_clk | Asserted when RX module has completed lane initialization. Typically connected to tx_aligned. |
| rx_bonded 3 | Output | user_clk | Asserted when RX module has completed channel bonding. Not used for single-lane channels. Typically connected to tx_bonded. |
| rx_verify 3 | Output | user_clk | Asserted when RX module has completed verification. Typically connected to tx_verify. |
| rx_reset 3 | Output | user_clk | Asserted when the RX module needs the TX module to restart initialization. Typically connected to tx_reset. |
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