The core requires a high-quality, low-jitter reference clock to drive the high-speed TX clock and clock recovery circuits in the transceivers. It also requires at least one frequency-locked parallel clock for synchronous operation with the user application. The Aurora 8B/10B core configures Channel Phase Locked Loop (CPLL) in AMD UltraScale™ and AMD UltraScale+™ families, Virtex 7, AMD Kintex™ 7, and AMD Zynq™ 7000 family designs.