The parameters used to generate each Aurora 8B/10B core determine the interfaces available for that
specific core. The interfaces are visible in the IP symbol as seen in the following figure.
In the IP symbol, if you left-click the + sign beside the interface, you can see the ports
grouped in it. In this section, that is, Port Descriptions, in general, the interface
appears as a single row entry followed by the ports which are grouped in it. For example in
the following table (TX) the
USER_DATA_S_AXIS_TX
is the interface and the s_axi_tx_* ports are grouped into that interface.
The cores have four to six interfaces.
Figure 1. IP Top-Level Interface

Note:
- [n:0] bus format is used when the Little Endian Support option is selected.
- [0:n] bus format is used when the Big Endian Support option is selected.
- Ports are active-High unless otherwise specified.