Lanes and Channel do not come up in simulation - 11.1 English - PG046

• The most effective method of debugging this condition is to view the signals from one instance of the serial transceivers that is not working.
• Make sure that the serial transceiver reference clock and user clocks are all toggling.
• Check to see that txoutclk from the serial transceiver wrapper is toggling. If not, it might take longer for the PMA to finish locking. Wait for lane up and channel up. It might take even longer for simplex designs.
• Make sure that txn and txp are toggling. If not, make sure to wait long enough and ensure that the TX signal is not being driven by another signal.
• Check the pll_not_locked signal in the design. If it is held active-High, the Aurora module is unable to initialize.
• Be sure the power_down signal is not asserted.
• If you assert rx_reset while using Timer mode and simplex configuration, you should also assert tx_reset to ensure that the core transmits the required initialization patterns for the rx_lane_up and rx_channel_up to come up.
• If you are using Verilog simulation, instantiate the glbl module and use it to drive the power_up reset at the beginning of the simulation. This procedure simulates the reset that occurs after configuration. Hold this reset for a few cycles.

The following code can be used an example:

//Simulate the global reset that occurs after configuration at
//the beginning
//of the simulation.
assign glbl.GSR = gsr_r;
assign glbl.GTS = gts_r;
initial
begin
gts_r = 1'b0;
gsr_r = 1'b1;
#(16*CLOCKPERIOD_1);
gsr_r = 1'b0;
end

If using a multi-lane channel, make sure all of the serial transceivers on each side of the channel are connected in the correct order.