| AMD LogiCORE™ IP Facts Table | |
|---|---|
| Core Specifics | |
| Supported Device Family 1 | AMD UltraScale+™ 2 , AMD UltraScale™ 2 , AMD Zynq™ 7000, 7 series 3 |
| Supported User Interfaces | AXI4-Stream |
| Resources | Performance and Resource Use web page |
| Provided with Core | |
| Design Files | Register Transfer Lever (RTL) |
| Example Design | Verilog and VHDL 2 |
| Test Bench | Verilog and VHDL 4 |
| Constraints File | Xilinx Design Constraints (XDC) |
| Simulation Model |
Source HDL with SecureIP transceiver simulation models |
| Supported S/W Driver 2 | N/A |
| Tested Design Flows 5 | |
| Design Entry | AMD Vivado™ Design Suite |
| Simulation | For supported simulators, see the Vivado Design Suite User Guide: Release Notes, Installation, and Licensing (UG973). |
| Synthesis | Vivado Synthesis |
| Support | |
| Release Notes and Known Issues | Master Answer Record: 54367 |
| All Vivado IP Change Logs | Master Vivado IP Change Logs: 72775 |
| Support web page | |
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