This appendix describes how to handle timing errors resulting from transceivers that are located far apart from each other. The Aurora 8B/10B core allows selecting any combination of transceiver(s) during core generation. The design parameters that affect the timing performance are:
- Line rate
- Transceiver datapath width (2/4 bytes)
- Number of unused transceivers between two selected transceivers
As a result of one or more of these parameters, timing errors can occur because:
- CHBONDO does not meet timing
- RXCHARISCOMMA, RXCHARISK, and RXCHANISALIGNED do not meet timing
The following suggestions can be attempted to meet timing:
- Select the transceivers consecutively.
Use the Lane Assignment in the Aurora 8B/10B AMD Vivado™ Integrated Design Environment (IDE) to select the transceivers during core generation.
- Most of the timing errors are due to unused transceivers and channel bonding signals connections among transceivers.
- Use the Strategies options provided for implementation in the Vivado Design Suite. See the Vivado Design Suite User Guide: Designing with IP (UG896) for instructions on how to use the Strategies options.