Generation of Aurora for Versal Devices - 11.1 English - PG046

Aurora 8B/10B LogiCORE IP Product Guide (PG046)
Document ID
PG046
Release Date
2025-12-18
Version
11.1 English

Vivado 2025.2 onwards, the Aurora 8b/10b IP supports Versal devices with PL-available GTs of type GTYE5 and GTYP. The following table lists the ports used in Versal families.

The IP generates Aurora without an embedded GT and moves the transceiver from the core to the support level in the example design. The following table lists the ports used to interface with the GT transceiver outside the Aurora IP.

Table 1. List of Ports to Interact with Versal GT Wizard
Name Direction Clock Description
gttxresetdone_in Input user_clk Active-High indication to Aurora that the transmitter reset sequence of transceiver primitives as initiated by the reset controller helper block is completed.
gtrxresetdone_in Input user_clk Active-High indication to Aurora that the transmitter reset sequence of transceiver primitives as initiated by the reset controller helper block is completed.
rxdata_in_lane Input user_clk User interface for data received per lane from transceiver.
rxnotintable_in_lane Input   Connect to rxctrl3 port of each lane of transceiver.
rxdisperr_in_lane Input   Connect to rxctrl1 port of each lane of transceiver.
rxchariscomma_in_lane Input   Connect to rxctrl2 port of each lane of transceiver.
rxcharisk_in_lane Input   Connect to rxctrl0 port of each lane of transceiver.
rxrealign_in_lane Input   Connects to rxbyterealign port of each lane of transceiver.
rxbuferr_in_lane Input   Connects to rxbufstatus port of each lane of transceiver.
txbuferr_in_lane Input   Connects to txbufstatus port of each lane of transceiver.
chbonddone_in_lane Input   Connects to rxchanisaligned port of each lane of transceiver.
rxbyteisaligned_in_lane Input   Connects to rxbyteisaligned port of each lane of transceiver.
txpd_out_lane Output   Connected to power_down signal
txelecidle_out_lane Output   Connected to power_down signal
txdetectrx_out_lane Output   Connected to power_down signal
rxchbondmaster_out_lane Output  

The master lane is driven to 1

The slave lanes are driven to 0.
rxchbondslave_out_lane Output  

The slave lanes are driven to 1

The master lane is driven to 0.
rxpd_out_lane Output   Connected to power_down signal
rxchbondlevel_out_lane Output  

Indicates the amount of internal pipelining used for the RX elastic buffer control signals.

Daisy chain pattern is followed with master lane having minimal value.
rxchbondo_in_lane Input   Connected to rxchbondo port of the corresponding lane of transceiver.
rxchbondi_out_lane Output   Connected to rxchbondi port of the corresponding lane of transceiver.
rxchanbonden_out_lane Output   Connected to rxchanbond_en port of each lane of transceiver.
rxchanbondbusy_in_lane Input   Connected to rxchanbond_busy port of each lane of transceiver.
rxpolarity_out_lane Output   Connected to rxpolarity port of each lane of transceiver.
txoutclk_in_lane Input   All the lanes are connected to master outclk from Versal GT wizard.
txcharisk_out_lane Output   Connected to txctrl2 port of each lane of transceiver.
txdata_out_lane Output   User interface for data transmitted per lane to transceiver.
Quad_gpi Output   Per quad signal connected to GPI port of transceiver.
Quad_gpo Input   Per quad signal connected to GPO port of transceiver.
gtwiz_reset_all_out Output   Connected to INTF0_rst_all_in port of Versal GT wizard.
gtwiz_reset_tx_datapath_out Output   Connected to INTF0_rst_tx_datapath_in port of Versal GT wizard.
gtwiz_reset_rx_datapath_out Output   Connected to INTF0_rst_rx_datapath_in port of Versal GT wizard.
gtwiz_reset_tx_pll_and_datapath_out Output   Connected to INTF0_rst_tx_pll_and_datapath_in port of Versal GT wizard.
gtwiz_reset_rx_pll_and_datapath_out Output   Connected to INTF0_rst_rx_pll_and_datapath_in port of Versal GT wizard.

For Versal family, block automation has been enabled for aurora IP. The following figure shows the connection between the aurora IP and Versal GT wizard through block automation.

Figure 1. Block Automation Connection for Versal Devices Generated by Your Tool
Note: When generating configurations with lanes not mapped serially in the Versal GT wizard, follow the steps to map according to chosen lanes:
  1. Update the Versal GT wizard xci to the required lane number.
  2. Update the pin names (outclk, usrclk, loopback) in the Versal GT wizard instance.
  3. Update the rxp, rxn, txp, txn pin connections according to chosen lane.
  4. Each quad generates GPI and GPO pins that are mapped to the quad lanes as follows (applies to GPO connections):
    1. GPI[8] -> lane 0
    2. GPI[9] -> lane 1
    3. GPI[10] -> lane 2
    4. GPI[11] -> lane 3

    Swap the pin connections to match the lane numbers selected in the Versal GT Wizard xci.