Click OK to generate the core. The modules for the Aurora 8B/10B core are written to the AMD Vivado™
design tools project directory using the same name as the top level of the core. See Output Generation for details about the example_design directory and files.
Note:
- In the IP integrator the Aurora 8B/10B core sets the expected frequency values in long format as per the IP integrator guidelines; however, internally the core precision is the same as shown in Vivado IDE.
- Data and flow control ports are grouped into AXI4-Stream interfaces. The other input and output ports are grouped into display interfaces.
- For the ports grouped in display interfaces the connections should be made manually.