The CRC module provides a 16-bit or 32-bit CRC, implemented for user data. The following tables describes the CRC module ports.
| Port Name | Direction | Clock Domain | Description |
|---|---|---|---|
| crc_valid | Output | user_clk | CRC valid port. When asserted High, enables sampling the crc_pass_fail_n signal. |
| crc_pass_fail_n | Output | user_clk | The crc_pass_fail_n signal is asserted High on transmit and receive when the CRC values for both the transmitter and receiver match. The crc_pass_fail_n signal should only be sampled with the crc_valid signal. |
See Using CRC for more information.