During power-on, the gt_reset and reset signals of
both the TX simplex and RX simplex cores are expected to be High. It is expected that INIT_CLK and GT_REFCLK are
stable during power-on. The gt_reset signal on the TX board
must be deasserted first, followed by the deassertion of gt_reset on the RX side; this ensures proper CDR lock on the RX side (see the
following figure).
Figure 1. Aurora 8B/10B Simplex Power On Reset Sequence
Simplex power-on sequence:
- Deassert TX-side
gt_reset(A) - Deassert RX-side
gt_reset(C) - Deassert RX-side rx_system_reset synchronous to
user_clk(D) - Deassert TX-side tx_system_reset synchronous to
user_clk(B)
Note: Care must be taken to ensure that the (D) to (B) time difference is
as minimal as possible.