For the simplex configuration, it is
recommended that the TX side reset sequence is tightly coupled with the RX side reset
sequence because the TX and RX links do not have a communication feedback path. Note
that if the RX side is reset, there is no direct mechanism to notify the TX side of the
reset. Hence, for Aurora 8B/10B simplex cores, reset coupling needs to be handled at the
system level. Every TX-side reset must be followed by the RX-side and, as shown in the
following figure, the time between RX-side reset deassertion and TX-side reset
deassertion must be kept as minimal as possible. Before asserting gt_reset , a minimum of 128 clock time period is required for ensuring
that the portion of the core in programmable logic reaches a known reset state before
the user_clk is suppressed by the assertion of c. The assertion time of gt_reset must be a minimum of six init_clk
time periods, to satisfy the de-bouncing circuit included in the core.
gt_reset and reset
de-assertion time between boardA and boardB should be kept as minimum as possible.
Failing to do can result in hard errors appearing on board where the reset is
de-asserted first. In such cases, hard error can be ignored.