During the board power-on
sequence, both gt_reset and reset signals must be High. The transceiver
reference clock (GT_REFCLK ) and the
core free running clocks (INIT_CLK ) are
expected to be stable during power-on for the proper functioning of
the Aurora 8B/10B core.
Figure 1. Aurora 8B/10B Duplex Power On Sequence
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gt_reset
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reset
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(boardA) INIT_CLK
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de-assert synchronous to user_clk
to user _clk
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de-assert synchronous to user_clk
to user _clk
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(boardB) INIT_CLK
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gt_reset
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reset
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X15654-120915
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