During normal operation, the
reset signal is expected to be asserted for at least 128
user_clk time period before assertion of the
gt_reset signal to ensure that the portion of the core in
programmable logic reaches a known reset state before the user_clk
signal is suppressed due to the assertion of gt_reset (see the
following figure).
Figure 1. Aurora 8B/10B Duplex Normal Operation Reset Sequence
