SPI Bus Transmit Waveform and Timing Budget - 4.1 English

Soft Error Mitigation Controller Product Guide (PG036)

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4.1 English

The SPI flash device has requirements on the switching characteristics of its input data with respect to its input clock. This analysis is for data capture at the SPI flash device, when receiving data from the system-level design example.

Figure 3-8: SPI Flash Device Input Data Capture Requirements

X-Ref Target - Figure 3-8


The following parameters, shown in This Figure , are defined as requirements for successful data capture by the SPI flash device:

T dvch = SPI flash minimum data setup requirement with respect to clock

T chdx = SPI flash minimum data hold requirement with respect to clock

The analysis assumes minimum propagation delays are zero. This analysis also assumes the following skews are negligible:

Skew on input clock distribution to FPGA output flip-flops.

Skew on output signal paths from FPGA output flip-flops to FPGA pins.

Skew in PCB level translator channel delays. The level translator on clock and datapaths must be matched for this to be true.

Skew in PCB trace segment delays. The trace delay on clock and datapaths must be matched for this to be true

Duty cycle distortion.

The following parameters are defined as implementation parameters of the EXT shim and PCB:

T clk = input clock cycle time ( icap_clk )

T qfpga = FPGA output delay with respect to icap_clk

T w1 = FPGA to level translator PCB trace delay

T w2 = Level translator to SPI flash PCB trace delay

T dly = Level translator channel delay

The memory system signaling generated by the EXT shim implementation is shown in This Figure .

Figure 3-9: Input Data Capture Timing

X-Ref Target - Figure 3-9


Given the stated assumptions, the delays on both the clock and datapaths are identical and track each other over process, voltage, and temperature variations. The following relationships exist:

T clk T dvch

T clk T chdx

Example :

T dvch = 2 ns (from SPI flash data sheet)

T chdx = 5 ns (from SPI flash data sheet)

1. Calculate: T clk T dvch requires T clk 2 ns

2. Calculate: T clk T chdx requires T clk 5 ns

These requirements on T clk indicate that the SPI Transmit Waveform and Timing Budget restrict the system-level design example input clock cycle time to be 5 ns or larger.