Revision History - 4.1 English - PG034

AXI Central Direct Memory Access LogiCORE IP Product Guide (PG034)
Document ID
PG034
Release Date
2025-07-11
Version
4.1 English

The following table shows the revision history for this document.

Section Revision Summary
07/11/2025 Version 4.1
Features Removed parameterized feature.
CDMACR (CDMA Control – Offset 00h) Added time-unit description for 31 to 24.
05/18/2022 Version 4.1
Overview
04/04/2018 Version 4.1
Overview
  • Updated the Enable CDMA Store and Forward option.
  • Updated Table 5.
04/05/2017 Version 4.1
Entire document IP updated to support DRE for data widths up to 512 bits.
10/05/2016 Version 4.1
Product Specification

Added a note about the AXI4-Lite write access register to the beginning of the Register Space section.
11/18/2015 Version 4.1
Introduction Added support for UltraScale+ families.
09/30/2015 Version 4.1
Additional Design Information
  • Added a note to AXI CDMA Register Summary.
  • Added Appendix C, Additional Design Information.
04/01/2015 Version 4.1
Entire document Added support for 64-bit addressing.
03/20/2013 Version 4.1
Introduction Updated for Vivado 2013.1, Zynq 7000, and 7 series FPGAs.
12/18/2013 Version 4.1
Introduction Added AMD UltraScale™ architecture support.
10/02/2013 Version 4.1
Product Specification
  • Revision number advanced to 4.1 to align with core version number.
  • Added example design with implementation and test bench sections
  • Modified Bit 6 in CDMACR register to be Cyclic BD Enable.
  • Updated screen display in Example Design.
  • Added Cyclic CDMA Mode section to Design Flow Steps.
  • Added IP integrator content to Example Design.
03/20/2013 Version 2.7
Entire document
  • Updated for Vivado 2013.1 design tool.
  • Removed information pertaining to Series 6 FPGAs.
  • Updated IP Facts table.
  • Updated Figure 1, AXI CDMA Block Diagram and supporting text.
  • Updated Table 1 and 15
  • Updated Figure 24 and supporting text.
  • Updated Master Answer Records information and Contacting Technical
  • Support and Debug Tools sections in Appendix B.
12/18/2012 Version 2.6
Debugging and Designing with the Core
  • Updated for Vivado 2012.4 and ISE v14.4 design tools.
  • Updated Table 1, Maximum Frequencies
  • Updated Debugging appendix.
  • Updated resource utilization tables: Tables 3, 4, and 5.
  • Removed Table 15, Reset Assertion/Deassertion Stabilization Times
  • Removed Parameter Descriptions section
  • Updated screen capture for Chapter 5 and removed one screen.
  • Removed material from the Output
10/16/2012 Version 2.5
Entire document
  • Updated for Vivado 2012.3 and ISE v14.3 design tools.
  • Document clean up.
07/25/2012 Version 2.0
Introduction
  • Updated for Vivado 2012.2, Zynq features, and ISE v14.2
  • Added Vivado content in Customizing and Generating the Core
07/11/2012 Version 1.1
Entire document Template update.
04/24/2012 Version 1.0
Entire document This new document is based on the LogiCORE IP AXI CDMA Product Specification (DS792).