An active-Low reset assertion on the
s_axi_lite_aresetn input results in a reset of the entire AXI CDMA core
logic. This is considered a hardware reset and there are no graceful completions of AXI4 transfers in progress. A hardware reset initializes all AXI CDMA registers
to the default state, all internal queues are flushed, and all internal logic is returned to
power on conditions. It is required that the s_axi_lite_aresetn input be
synchronous to the s_axi_lite_aclk input.
Note: Reset must be asserted for a minimum of 16 clock
cycles to the core to take effect.