| AMD LogiCORE™ IP Facts Table | |
|---|---|
| Core Specifics | |
| Supported Device Family 1 |
AMD Versal™
adaptive SoC AMD UltraScale+™ AMD UltraScale™ AMD Zynq™ 7000 SoC AMD 7 series FPGAs |
| Supported User Interfaces | AXI4, AXI4-Lite |
| Resources | Performance and Resource Use web page |
| Provided with Core | |
| Design Files | VHDL |
| Example Design | VHDL |
| Test Bench | VHDL |
| Constraints File | Xilinx Design Constraints (XDC) delivered with IP generation |
| Simulation Model | Not Provided |
| Supported S/W Driver 2 | Standalone and Linux |
| Tested Design Flows 3 | |
| Design Entry | AMD Vivado™ Design Suite |
| Simulation | For supported simulators, see the Vivado Design Suite User Guide: Release Notes, Installation, and Licensing (UG973). |
| Synthesis | Xilinx Synthesis Technology (XST) AMD Vivado™ Synthesis |
| Support | |
| Release Notes and Known Issues | Master Answer Record: 54685 |
| All Vivado IP Change Logs | Master Vivado IP Change Logs: 72775 |
| Support web page | |
|
|