CDMACR (CDMA Control – Offset 00h) - 4.1 English - PG034

AXI Central Direct Memory Access LogiCORE IP Product Guide (PG034)

Document ID: PG034
Release Date: 2025-07-11
Version: 4.1 English

This register provides software application control of the AXI CDMA.

Figure 1. CDMACR Register

Table 1. CDMACR Register Details
Bits	Field Name	Default Value	Access Type	CDMA Mode Used	Description
31 to 24	IRQDelay	00h	R/W	SG	Interrupt Delay Timeout. This value is used for setting the interrupt delay timeout value. The interrupt timeout is a mechanism for causing the CDMA engine to generate an interrupt after the delay time period has expired. Timer begins counting at the end of a packet and resets with the receipt of a new packet or a timeout event occurs.⁽³⁾⁽⁴⁾ 1 Timeout Interval = 125(IRQDelay_Value) (clock period of SG clock) Setting a value of 3 results in a delay timeout of 125 x 3 x (clock period of SG clock).
23 to 16	IRQThreshold	01h	R/W	SG	Interrupt Threshold. This value is used for setting the interrupt threshold. When IOC interrupt events occur, an internal counter counts down from the Interrupt Threshold setting. When the count reaches zero, an interrupt out is generated by the DMA engine.⁽⁵⁾⁽⁶⁾
15	Reserved	0	RO	N/A	Writing to this bit has no effect and it is always read as zeros.
14	Err_IrqEn	0	R/W	Simple and SG	Error Interrupt Enable. When set to 1, it allows the CDMASR.Err_Irq to generate an interrupt out. 0 = Error Interrupt disabled 1 = Error Interrupt enabled
13	Dly_IrqEn	0	R/W	SG	Delay Timer Interrupt Enable. When set to 1, it allows CDMASR.Dly_Irq to generate an interrupt out. This is only used with Scatter Gather assisted transfers. 0 = Delay Interrupt disabled 1 = Delay Interrupt enabled
12	IOC_IrqEn	0	R/W	Simple and SG	Complete Interrupt Enable. When set to 1, it allows CDMASR.IOC_Irq to generate an interrupt out for completed DMA transfers. 0 = IOC Interrupt disabled 1 = IOC Interrupt enabled
11 to 7	Reserved	0	RO	N/A	Writing to these bits has no effect and they are always read as zeros.
6	Cyclic BD Enable	0	R/W	SG	When set to 1, you can use the CDMA in Cyclic Buffer Descriptor (BD) mode without any user intervention. In this mode, the Scatter Gather module ignores the Completed bit of the BD. With this feature, you can use the same BDs in cyclic manner without worrying about any errors. This bit must be set before updating the TAILDESC register. Changing this bit while the transfer is in progress will generate undefined results.
5	Key Hole Write	0	R/W	Simple and SG	Writing 1 to this enables the keyhole write (FIXED address AXI transaction). This value must not be changed when a transfer is in progress. This value must remain constant until all the descriptors are processed (for SG = 1). CDMA shows unexpected behavior if this value is changed in the middle of a transfer. It is the responsibility of the slave device to enforce the functionality. When enabling Key Hole operation, the MAX BURST LENGTH must be set to 16.
4	Key Hole Read	0	R/W	Simple and SG	Writing 1 to this enables the keyhole read (FIXED address AXI transaction). This value must not be changed when a transfer is in progress. This value must remain constant until all the descriptors are processed (for SG = 1). CDMA shows unexpected behavior if this value is changed in the middle of a transfer. It is the responsibility of the slave device to enforce the functionality. When enabling Key Hole operation, the MAX BURST LENGTH must be set to 16.
3	SGMode	0	R/W	Simple and SG	This bit controls the transfer mode of the CDMA. Setting this bit to a 1 causes the AXI CDMA to operate in a Scatter Gather mode if the Scatter Gather engine is included. 0 = Simple DMA Mode 1 = Scatter Gather Mode This bit must only be changed when the CDMA engine is idle (CDMASR.IDLE = 1). Changing the state of this bit at any other time has undefined results. This bit must be set to a 0 then back to 1 by the software application to force the CDMA SG engine to use a new value written to the CURDESC_PNTR register. This bit must be set prior to setting the CDMACR.Dly_IrqEn bit. Otherwise, the CDMACR.Dly_IrqEn bit does not get set.
2	Reset	0	R/W	Simple and SG	Soft reset control for the AXI CDMA core. Setting this bit to a 1 causes the AXI CDMA to be reset. Reset is accomplished gracefully. Committed AXI4 transfers are then completed. Other queued transfers are flushed. After completion of a soft reset, all registers and bits are in the Reset State. 0 = Reset NOT in progress – Normal operation 1 = Reset in progress
1	TailPntrEn	1	RO	SG	Indicates tail pointer mode is enabled in the SG Engine. This bit is fixed to 1 and always read as 1 when SG is included. If the CDMA is built with SG disabled (Simple Mode Only), the default value of the port is 0.
0	Reserved	0	RO	N/A	Writing to these bits has no effect, and they are always read as zeros.
RO = Read Only. Writing has no effect. R/W = Read/Write Setting this value to zero disables the delay timer interrupt. This is irrelevant when Scatter Gather is excluded. The minimum setting for the threshold is 0x01. A write of 0x00 to this register has no effect. This is irrelevant when Scatter Gather is excluded.