The core is designed to integrate with the 7 series FPGA transceiver. This Figure illustrates the connections and logic required between the core and the transceiver; the signal names and logic in the figure precisely match those delivered with the example design when a 7 series FPGA transceiver is used.
The 125 MHz differential reference clock is routed directly to the 7 series transceiver. The transceiver is configured to output a version of this clock (125 MHz) on the txoutclk port; this is then placed onto global clock routing and is input back into the GTXE2 transceiver on the user interface clock ports txusrclk and txusrclk2 . This clock is also used to source for all core logic.
The transceiver is configured to output a recovered clock (125 MHz) on the rxoutclk port; this is placed onto global routing through BUFG. This clock is then used to source the receive logic from Transceiver receive side output to the rxelastic buffer in the core. The clocking logic is included in a separate module, <component_name>_clocking , which is instantiated in the <component_name>_support module.
The two wrapper files immediately around the GTP transceiver pair, gtwizard and gtwizard_gt ( This Figure ), are generated from the 7 series FPGA transceiver wizard. These files apply all the QSGMII attributes. Consequently, these files can be regenerated by invoking the 7 series FPGAs transceivers wizard in the Vivado Design Suite and selecting the QSGMII Protocol template on the Line Rate, RefClk Selection tab. For more information, see the 7 Series FPGAs GTX/GTH Transceivers User Guide (UG476) [Ref 5] .
Note: The optional Transceiver Control and Status ports are not shown here. These ports are brought up to the <component_name> module level.