This Figure illustrates sharing clock resources across two instantiations of the core when using 7 series FPGAs transceivers. Additional cores can be added by continuing to instantiate extra block level modules. One instance of the core is generated with the Include Shared Logic in Core option. This instance contains all the clocking logic that can be shared.
The remaining instances can be generated using the Include Shared Logic in Example Design option. This method of using shared logic core is limited to a GT Quad.
To provide the FPGA logic clocks for all core instances, select a txoutclk port from any transceiver and place it onto global clock routing using BUFGs; these can be shared across all core instances and transceivers as illustrated,
Each GTX transceiver and core pair instantiated has its own independent clock domains synchronous to rxoutclk . These are placed on global clock routing using a BUFG, as illustrated in This Figure , and cannot be normally shared across multiple transceivers. The clocking logic for rxoutclk can only be shared if it is known that the transceiver and core pairs across QSGMII instances are synchronous. In this case the receive clock outputs of clocking module can be used.
.
