This Figure in Appendix C illustrates the GMII input logic provided in the core for the Zynq 7000 SoC, Virtex 7, Kintex 7, and Artix 7 family.
This Figure in Appendix C illustrates the MII input logic provided in the core for the Zynq 7000 SoC, Virtex 7, Kintex 7, and Artix 7 family.
IODELAY elements are instantiated on the GMII/MII data input path as illustrated. Fixed tap delays are applied to these IODELAY elements to delay the GMII/MII input data signals so that data is correctly sampled at the IOB IDDR registers, thereby meeting GMII/MII input setup and hold timing constraints.
The number of tap delays are applied using the following XDC syntax.
#***********************************************************
# To Adjust GMII Tx Input Setup/Hold Timing *
#***********************************************************
# These constraints will be set at a later date when device speed files have matured
set_property IDELAY_VALUE 0 [get_cells delay_gmii_tx_en_ch0]
set_property IDELAY_VALUE 0 [get_cells delay_gmii_tx_er_ch0]
set_property IDELAY_VALUE 0 [get_cells {gmii_data_bus_ch0[7].delay_gmii_txd_ch0}]
set_property IDELAY_VALUE 0 [get_cells {gmii_data_bus_ch0[6].delay_gmii_txd_ch0}]
set_property IDELAY_VALUE 0 [get_cells {gmii_data_bus_ch0[5].delay_gmii_txd_ch0}]
set_property IDELAY_VALUE 0 [get_cells {gmii_data_bus_ch0[4].delay_gmii_txd_ch0}]
set_property IDELAY_VALUE 0 [get_cells {gmii_data_bus_ch0[3].delay_gmii_txd_ch0}]
set_property IDELAY_VALUE 0 [get_cells {gmii_data_bus_ch0[2].delay_gmii_txd_ch0}]
set_property IDELAY_VALUE 0 [get_cells {gmii_data_bus_ch0[1].delay_gmii_txd_ch0}]
set_property IDELAY_VALUE 0 [get_cells {gmii_data_bus_ch0[0].delay_gmii_txd_ch0}]
set_property IDELAY_VALUE 0 [get_cells delay_gmii_tx_en_ch1]
set_property IDELAY_VALUE 0 [get_cells delay_gmii_tx_er_ch1]
set_property IDELAY_VALUE 0 [get_cells {gmii_data_bus_ch1[7].delay_gmii_txd_ch1}]
set_property IDELAY_VALUE 0 [get_cells {gmii_data_bus_ch1[6].delay_gmii_txd_ch1}]
set_property IDELAY_VALUE 0 [get_cells {gmii_data_bus_ch1[5].delay_gmii_txd_ch1}]
set_property IDELAY_VALUE 0 [get_cells {gmii_data_bus_ch1[4].delay_gmii_txd_ch1}]
set_property IDELAY_VALUE 0 [get_cells {gmii_data_bus_ch1[3].delay_gmii_txd_ch1}]
set_property IDELAY_VALUE 0 [get_cells {gmii_data_bus_ch1[2].delay_gmii_txd_ch1}]
set_property IDELAY_VALUE 0 [get_cells {gmii_data_bus_ch1[1].delay_gmii_txd_ch1}]
set_property IDELAY_VALUE 0 [get_cells {gmii_data_bus_ch1[0].delay_gmii_txd_ch1}]
The number of tap delays are preconfigured in the example designs to meet the setup and hold constraints for the example GMII/MII pinout in the particular device.