Virtex 7 FPGA GTH Transceivers - 4.0 English - PG029

The constraints defined in this section are implemented in the XDC for the example designs delivered with the core. Sections from the XDC are copied into the following descriptions to serve as examples and should be studied with the HDL source code for the example design. For more information, see the 7 Series FPGAs GTX/GTH Transceivers User Guide (UG476).

Transceiver Placement Constraint

The provided XDC uses placement constraints to specify the serial transceiver that is used when the core is implemented. This can be moved around according to the application.

set_property LOC GTHE2_CHANNEL_X0Y4 [get_cells */*/*/transceiver_inst/gtwizard_inst/*/GTWIZARD_i/gt0_GTWIZARD_i/gthe2_i

Clock Period Constraints

The gtrefclk clock is provided to the GTH transceiver. It is a high-quality reference clock with a frequency of 125 MHz and should be constrained.

#***********************************************************
# PCS/PMA Clock period Constraints: please do not relax *
#***********************************************************
create_clock -add -name gtrefclk -period 8.000 [get_ports gtrefclk_p]

GTH Transceiver Attributes

The Virtex 7 FPGA GTH transceiver has many attributes that are set directly from the HDL source code for the transceiver wrapper file delivered with the example design. These can be found in the gtwizard_gt.vhd file (for VHDL design entry) or the gtwizard_gt.v file (for Verilog design entry); these files were generated using the 7 series FPGA transceiver wizard. To change the attributes, re-run the wizard.