The constraints defined in this section are implemented in the XDC for the example designs delivered with the core. Sections from the XDC are copied into the following descriptions to serve as examples and should be studied with the HDL source code for the example design.
Transceiver Placement Constraint
The provided XDC uses placement constraints to specify the serial transceiver that is used when the core is implemented. This can be moved around according to the application.
set_property LOC GTY_QUAD_X0Y3 [get_cells -hier -filter {name =~ */gt_quad_base*/inst/quad_inst}]
set_property LOC GTY_REFCLK_X0Y6 [get_cells -hier -filter {name =~ */util_ds_buf*/U0/USE_IBUFDS_GTE5.GEN_IBUFDS_GTE5[0].IBUFDS_GTE5_I}]Clock Period Constraints
The gtrefclk
clock is provided to the GTY transceiver. It is a high-quality reference clock with
a frequency of 125 MHz and should be constrained.
#***********************************************************
# PCS/PMA Clock period Constraints: please do not relax *
#***********************************************************
create_clock -add -name gtrefclk -period 8.000 [get_ports gtrefclk_p]