This chapter provides general guidelines for using transceivers with AMD UltraScale+™ families, AMD UltraScale™ architecture, AMD Zynq ™ 7000 SoC, AMD Virtex ™ 7, AMD Kintex ™ 7, or AMD Artix ™ 7 devices and is organized into the following main sections, with each section being organized into FPGA families.
Providing a more detailed look at the device-specific transceivers and their connections to the netlist of the core.
• Clock Sharing Across Multiple Cores with Transceivers
Providing guidance for using several cores and transceiver instantiations; clock sharing should occur whenever possible to save device resources.