Upgrading in the Vivado Design Suite - 4.0 English - PG029

Quad Serial Gigabit Media Independent LogiCORE IP Product Guide (PG029)
Document ID
PG029
Release Date
2025-12-09
Version
4.0 English

This section provides information about any changes to the user logic or port designations between core versions.

In the v3.0 of the core, there are several changes that make the core pin-incompatible with the previous version(s). These changes were required as part of the general one-off hierarchical changes to enhance the customer experience and are not likely to occur again.

Shared Logic

As part of the hierarchical changes to the core, it is now possible to have the core itself include all of the logic that can be shared between multiple cores, which was previously exposed in the example design for the core.

If you are updating a previous version to the v3.0 with Shared Logic, there is no simple upgrade path; it is recommended to consult the Shared Logic sections of this document for more guidance.

Port Changes from v3.3 to v3.4

Between QSGMII v4.3 and QSGMII v4.4, a single output port, gt_powergood_out was added. This signal indicates that CPLL calibration has been completed in the GTWIZARD. This signal should be tied to CE pin of BUFG_GT if used, otherwise, left open.

Port Changes from v3.2 to v3.3

The following ports were added to the core, but only if the Transceiver Debug feature was requested during core customization. Consult the relevant transceiver user guide for more information on using these control/status ports.

Ports Added

Port Name and Width In/Out Description What to do
gt0_txinhibit_in Input Inhibits transmission If not used, should be tied off as specified in the transceiver guide.
gt_pcsrsvdin[15:0] Input DRP Reset. Available only for UltraScale/UltraScale+ devices. If not used, should be tied off as specified in the transceiver guide.

Port Changes from v3.0 to v3.1

The following ports were added to the core, but only if the Transceiver Debug feature was requested during core customization. Consult the relevant transceiver user guide for more information on using these control/status ports.

Ports Added

Port Name and Width In/Out Description What to do
gt0_rxlpmreset_in Input RX LPM Reset (valid only for GTP transceivers) If not used, should be tied off as specified in the transceiver guide.
gt0_rxlpmhfovrden_in Input Valid only for GTP transceivers  
gt0_dmonitorout_out[16:0] Output Digital Monitor to monitor state of LPM/DFE loops  
gt0_gttxreset_in Input Reset to start full transmit reset sequence. Present in only non UltraScale devices.  
gt0_txpcsreset_in Input Reset for TX PCS  
gt0_txpmareset_in Input Reset for TX PMA  
gt0_gtrxreset_in Input Reset to start full receive reset sequence. Present in only non UltraScale devices.  
gt0_rxpcsreset_in Input Reset for RX PCS  
gt0_rxpmareset_in Input Reset for RX PMA  
gt0_rxpmaresetdone_out Output Indication that RX PMA reset sequence is complete. Available only for non GTX transceivers.  
gt0_cplllock_out Output Indication that CPLL has locked  
gt0_txbufstatus_out[1:0] Output Indicates the status of TX buffer  

Port Changes from v2.0 to v3.0

Between QSGMII v4.3 and QSGMII v4.4, a single output port, gt_powergood_out was added. This signal indicates that CPLL calibration has been completed in the GTWIZARD. This signal should be tied to CE pin of BUFG_GT if used, otherwise, left open.

Ports Added

The following ports were added to the core (non-shared logic).

Ports Added (Non-Shared Logic)

Port Name and Width In/Out Description What to do
rxoutclk Output rxoutclk from the Transceiver

This was previously connected internally to clocking elements and routed to rxuserclk and rxuserclk2 .

This can be left open if rxoutclk can be shared across instances or if not should drive clocking elements.
rxuserclk Input Signal from the shared logic block to the transceiver If rxoutclk can be shared across instances, connect O/P of shared logic block. If not connect to rxoutclk after passing through additional clocking elements.
rxuserclk2 Input Signal from the shared logic block to the transceiver If rxoutclk can be shared across instances, connect O/P of shared logic block. If not connect to rxoutclk after passing through additional clocking elements.
gt0_pll0outclk_in Input Valid only for AMD Artix 7 families. Indicates out clock from PLL0 of GT Common. Should be connected to signal of same name from GT Common
gt0_pll0outrefclk_in Input Valid only for Artix 7 families. Indicates reference out clock from PLL0 of GT Common. Should be connected to signal of same name from GT Common
gt0_pll1outclk_in Input Valid only for Artix 7 families. Indicates out clock from PLL1 of GT Common. Should be connected to signal of same name from GT Common
gt0_pll1outrefclk_in Input Valid only for Artix 7 families. Indicates reference out clock from PLL1 of GT Common. Should be connected to signal of same name from GT Common
gt0_pll0lock_in Input Valid only for Artix 7 families. Indicates out PLL0 of GT Common has locked. Should be connected to signal of same name from GT Common
gt0_pll0refclklost_in Input Valid only for Artix 7 families. Indicates out reference clock for PLL0 of GT Common is lost. Should be connected to signal of same name from GT Common
gt0_pll0reset_out output Valid only for Artix 7 families. Reset for PLL of GT Common from reset fsm in GT Wizard Should be connected to signal of same name from GT Common or can be left open if not needed
gt0_qplloutclk_in Input Valid only for non Artix 7 families. Indicates out clock from PLL of GT Common. Should be connected to signal of same name from GT Common
gt0_qplloutrefclk_in Input

Valid only for non Artix 7

Families. Indicates reference out clock from PLL of GT Common.

 Should be connected to signal of same name from GT Common

The following ports were added to the core, but only if the transceiver debug feature was requested during core customization. Consult the relevant transceiver user guide for more information on using these control/status ports.

Ports Added for Transceiver Debug Feature

Port Name and Width In/Out Description What to do
gt0_rxchariscomma_out[3:0] Output RX Character is Comma indication If you want to be more compatible with the previous version of the core and also if DRP interface was not used, do not request the Transceiver Debug feature.
gt0_rxcharisk_out[3:0] Output RX Character is K indication  
gt0_rxbyteisaligned_out Output RX Byte is aligned indication  
gt0_rxbyterealign_out Output RX Byte is realigned indication  
gt0_rxcommadet_out Output RX Comma is detected indication  
gt0_txpolarity Input Switch the sense of the TXN/P pins If you want to be more compatible with the previous version of the core and also if DRP interface was not used, do not request the Transceiver Debug feature. Otherwise, drive this signal according to the relevant transceiver user guide.
gt0_txdiffctrl[3:0] Input Can be used to tune the transceiver TX waveform  
gt0_txprecursor[4:0] Input Can be used to tune the transceiver TX waveform  
gt0_txpostcursor[4:0] Input Can be used to tune the transceiver TX waveform  
gt0_rxpolarity Input Switch the sense of the RXN/P pins  
gt0_txprbssel_in[2:0] Input TX Pattern Generator control signals to test signal integrity  
gt0_txprbsforceerr_in Input TX Pattern Generator control signals to test signal integrity  
gt0_rxprbscntreset_in Input RX Pattern Checker reset  
gt0_rxprbserr_out Output RX Pattern Checker error output  
gt0_rxprbssel_in[2:0] Input RX Pattern Checker control signals to test signal integrity  
gt0_loopback_in[2:0] Input Loopback within transceiver  
gt0_txresetdone_out Output Transmitter Reset Done  
gt0_rxresetdone_out Output Receiver Reset Done  
gt0_rxdisperr_out[3:0] Output Indicates there is disparity error in received data  
gt0_rxnotintable_out[3:0] Output Indicates received 10 bit pattern was not found in 8B/10B decode table  
gt0_eyescanreset Input Reset the EYE Scan logic  
gt0_eyescantrigger Input Trigger the EYE Scan logic  
gt0_eyescandataerror Output Signals an error during Eye Scan  
gt0_rxrate[2:0] Input Change the PLL Divider value  
gt0_rxcdrhold Input Freeze the CDR loop  
gt0_rxcdrlock_out Output CDR loop has locked  
gt0_rxratedone_out Output Asserted in response to change in RXRATE  
gt0_rxlpmhfhold_in Input GTP Low power mode signal  
gt0_rxlpmlfhold_in Input GTP Low power mode signal  
gt0_rxmonitorout_out[6:0] Output GTX/GTH RX DFE Signal  
gt0_rxmonitorsel_in[1:0] Input GTX/GTH RX DFE Signal  

Ports Moved

The following ports were moved under the Transceiver Debug Feature of the core (non-shared logic). If these signals were used in the previous version, the Transceiver Debug feature needs to be enabled and the appropriate signals mapped and remaining signals tied off to default values as specified in the relevant transceiver user guide.

Ports Moved (non-shared logic)

In/Out Port Name and Width Description What to do
Outputs

gt0_drp_busy_out,

gt0_drpdo_out, gt0_drprdy_out

 These signals come from the transceiver and should be connected either to an external arbiter or to the signals described in the next row. If there is no external arbiter, connect these signals directly to the associated signals. If they interface is not used. Can be left open.
Inputs

gt0_drpen_in, gt0_drpwe_in, gt0_drpaddr_in[8:0], gt0_drpdi_i[15:0],

gt0_drpclk_in

 These signals go to the transceiver, either from an external arbiter or from the signals described in the previous row. If there is no external arbiter, connect these signals directly to the associated core signals. If the interface is not used, tie off the signals to ground and gt0_drpclk_in to txusrclk2.

Ports Removed

The following ports were removed from the core interface and are driven internally in the core.

Ports Removed

In/Out Port Name and Width Description What to do
Input link_timer_value_chx[8:0] Used to configure the duration of the Auto-Negotiation Link Timer period. The duration of this timer is set to the binary number input into this port multiplied by 4096 clock periods of the 125 MHz reference clock (8 ns). For normal operation the value of link timer is set internally to "000110010" as specified in QSGMII specification for 1.6 ms link time. To speed up simulation this value can be set internally to "000000100." This is done though xci file by the parameter EXAMPLE_SIMULATION.