QSGMII Operating in MAC Mode
This module accepts transmitter data from the GMII-style
interface from the attached client MAC and samples the input data on the 125 MHz reference
clock, clk125m. This sampled data can then be connected directly to the
input GMII instances of the QSGMII netlist. The 1 Gb/s and 100 Mb/s cases are illustrated in
the following figure.
At all speeds, the client MAC logic should drive the GMII
transmitter data synchronously to the rising edge of the 125 MHz reference clock while using
sgmii_clk_en (derived from the Clock Generation module) as a clock
enable. The frequency of this clock enable signal ensures the correct data rate and correct
data sampling between the two devices.
QSGMII Operating in PHY Mode
QSGMII in PHY mode follows the true GMII/MII interface. When
the GMII interface is selected, the data is received on the 125 MHz clock
(clk125m). When the MII interface is selected, 4 bits of MII are received
on the least significant bit (LSB) 4 bits of the GMII interface. This interface is converted
to 8 bits by sampling with sgmii_ddr_clk_en (derived from the Clock
Generation module).
This 8-bit interface should drive the GMII transmitter data
synchronously to the rising edge of the 125 MHz reference clock while using
sgmii_clk_en (derived from the Clock Generation module) as a clock
enable.
It is possible that the Start of Frame Delimiter (SFD) could be skewed across two separate bytes, so 8-bit SFD code is detected, and if required, it is realigned across the 8-bit datapath.
The 1 Gb/s and 100 Mb/s cases are illustrated in the following figure.